1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same and, more particularly, to a semiconductor device having a COB type DRAM and to a method of manufacturing the same
2. Description of the Prior Art
In recent DRAM, the COB (Capacitor Over Bit-line) type in which an information storage capacitor is arranged on a bit line connected to a transistor is used, and a logic circuit is often also formed on the same substrate on which the transistor and capacitor are formed. A wiring structure in a memory cell region and a peripheral circuit region of the COB type DRAM is shown in a plan view of FIG. 1, for example.
In FIG. 1, a memory cell region 101 and a peripheral circuit region 102 are arranged on a semiconductor substrate 100.
A plurality of active regions 103 are surrounded and partitioned by a device isolation insulating layer 104 in the memory cell region 101 of the semiconductor substrate 100. A plurality of word lines that are also used as gate electrodes formed on the active regions 103 via a gate insulating film (not shown). Also, impurity diffusion layers 103a, 103b serving as source/drain are formed on both sides of the word line 105 in the active regions 103. Accordingly, a plurality of MOS transistors are formed in the active regions 103.
A plurality of bit lines 106 are formed on the word lines 105 via a first interlayer insulating film (not shown), and the bit lines 106 and the word lines 105 are extended to intersect orthogonally with each other.
The bit line 106 is connected to the active region 103 via a contact hole 107 formed in the first interlayer insulating film. The impurity diffusion layer 103a put between two word lines 105 is located at a position to which the bit line 106 is connected. Also, storage electrodes (not shown) of a capacitor 108, that is formed on the bit line 106 via a second interlayer insulating film (not shown), are connected to the impurity diffusion layers 103b located near both ends of the active region 103. The storage electrodes are connected to the impurity diffusion layers 103b via storage contact holes 109 formed in the first and second interlayer insulating films.
An active region 110 is surrounded and partitioned by the device isolation insulating film 104 in the peripheral circuit region 102. A gate electrode 111 is formed on the active region 110 via a gate insulating film (not shown). Also, impurity diffusion layers 112a, 112b serving as source/drain are formed on both sides of the gate electrode 111 in the active region 110 of the semiconductor substrate 100. Accordingly, a MOS transistor is formed in the active region 110.
A first wiring 106a is formed integrally with the bit line 106 in the memory cell region 101 of the peripheral circuit region 102. The first wiring 106a is connected to one impurity diffusion layer 112a in the active region 110 via a contact hole 128b. Also, a second wiring 113 is connected to the other impurity diffusion layer 112b via a contact hole 128c. 
In FIG. 1, a reference 114 denotes a lower wiring that has the almost same height as the gate electrode 111 in the peripheral circuit region 102. A third wiring 115 formed in the same layer as the second wiring 113 is connected onto the lower wiring 114.
Various structures of the bit lines 106, the wirings 106a, 113, 115 shown in FIG. 1 are known. Then, these structures will be explained hereunder.
FIG. 2 is sectional view showing a semiconductor device having the DRAM and the peripheral circuit. The same references as those in FIG. 1 denote the same elements. FIG. 2 shows a sectional shape taken along a Ixe2x80x94I line in FIG. 1 and a sectional shape taken along a IIxe2x80x94II line.
In FIG. 2, a plurality of active regions 103 are surrounded and partitioned by the device isolation insulating layer 104 in the memory cell region 101 of the semiconductor substrate 100. A plurality of MOS transistors are formed in these active regions 103.
Upper and side surfaces of a plurality of word lines (gate electrodes) 105, that are formed on the active regions 103 via the gate insulating film 105a, are covered with insulating films 121, 122. Also, impurity diffusion layers 103a, 103b serving as source/drain are formed on both sides of the word lines 105 in the active regions 103.
Also, the active region 110 is formed in the peripheral circuit region 102 to be surrounded by the device isolation insulating layer 104. A MOS transistor is formed in the active region 110. More particularly, the gate electrode 111 is formed in the active region 110 of the semiconductor substrate 100 via the gate insulating film 111a, and the impurity diffusion layers 112a, 112b serving as source/drain are formed on both sides of the gate electrode 111. Insulating films 121, 122 are formed on an upper surface and side surfaces of the gate electrode 111. In addition, a lower wiring 114 is formed on the device isolation insulating layer 104 in the peripheral circuit region 102.
A first interlayer insulating film 123 is formed on the semiconductor substrate 100 to cover the MOS transistor. Also, contact holes are formed in the first interlayer insulating film 123 on the impurity diffusion layers 103a, 103b in the memory cell region 101 respectively. First and second contact plugs 125a, 12b are formed in these contact holes. The first contact plug 125a is connected to the impurity diffusion layer 103a formed between the word lines 105, and the second contact plugs 125b are connected to the impurity diffusion layers 103b near both ends of the active regions 103.
A second interlayer insulating film 126 is formed on the first interlayer insulating film 123. A plurality of wiring trenches (recesses) 127a, 127b, 127c and a plurality of contact holes 128a, 128b, 128c, 128d are formed in the first interlayer insulating film 123 and the second interlayer insulating film 126 by the dual damascene method.
The wiring trenches 127a, 127b, 127c formed in the second interlayer insulating film 126 have a shape of the bit line 106 in the memory cell region 101 and shapes of the wirings 106a, 113, 115 in the peripheral circuit region 102 respectively.
The contact hole 128a located in the memory cell region 101 is formed to reach the first contact plug 125a from a bottom of the wiring trench 127a. The contact holes 128b, 128c, 128d are formed to reach the impurity diffusion layers 112a, 112b and the lower wiring 114 from bottoms of the wiring trenches 127a, 127b, 127c respectively.
A barrier metal layer and a tungsten layer are buried in sequence in a plurality of wiring trenches 127a, 127b, 127c and a plurality of contact holes 128a, 128b, 128c, 128d. The barrier metal layer and the tungsten layer formed on the second interlayer insulating film 126 are removed by the chemical mechanical polishing (CMP) method.
Accordingly, in the memory cell region 101, the bit line 106 made of a tungsten film is formed in the second interlayer insulating film 126 and also the bit line 106 is connected to the first contact plug 125a on the active region 103 via the contact hole 128a. Also, in the peripheral circuit region 102, the first, second and third wirings 106a, 113 and 115 made of the tungsten film are formed in the second interlayer insulating film 126. These wirings 106a, 113 and 115 are connected the impurity diffusion layers 112a, 112b and the lower wiring 114 via the contact holes 128b, 128c, 128d respectively.
A third interlayer insulating film 129 is formed on the bit line 106, the wirings 106a, 113, 115 and the second interlayer insulating film 126.
Storage contact holes 109 reaching upper surfaces of the second contact plugs 125b are formed in the first, second and third interlayer insulating film 123, 126, 129 in the memory cell region 101. Storage contact plugs 131 are formed in the storage contact holes 109. The storage, contact holes 109 are formed to reach the second contact plugs 125b while passing through between a plurality of bit lines 106.
A silicon nitride film 132 is formed on the third interlayer insulating film 129. Openings whose size corresponds to the storage electrode of the capacitor are formed in the silicon nitride film 132 in the memory cell region 101. Cylindrical storage electrodes 133 are formed upwardly from the openings. Also, a dielectric film 134 is formed on surfaces of the storage electrodes 133. An opposing electrode (cell plate) 135 is formed on the dielectric film 134. Thus, the capacitor 108 consists of the storage electrodes 133, the dielectric film 134, and the opposing electrode 135. After such the capacitors 108 are formed, the dielectric film 134 and the opposing electrode 135 are removed from the peripheral circuit region 102 by the photolithography method.
Also, a fourth interlayer insulating film 136 is formed on the third interlayer insulating film 129 to cover the capacitors 108. A plurality of contact holes 137a, 137b, 137c reaching the first, second, and third wirings 106a, 113, 115 respectively are formed in the fourth interlayer insulating film 136 in the peripheral circuit region 102. Plugs 138a, 138b, 138c formed of a barrier metal film and a tungsten film are buried in these contact holes 137a, 137b, 137c respectively.
In addition, aluminum wirings 139a, 139b, 139c connected to the plugs 138a, 138b, 138c respectively are formed on the fourth interlayer insulating film 136.
The first, second, third, and fourth interlayer insulating film 123, 126, 129, 136 are formed of a silicon oxide or impurity containing silicon oxide.
In the mentioned-above semiconductor device, there is the possibility that, if pitches between the bit lines 106 are narrowed with the miniaturization of the memory cell, the storage contact plugs 131 come into contact with the bit lines 106 because of the slight displacement of the storage contact holes 109 that pass through between the bit lines 106. That is, the semiconductor device has a structure in which the storage contact plugs 131 cannot be formed in the self-align fashion with the bit lines 106.
In contrast, shown in FIG. 3, it is set forth in Symposium on VLSI Technology, pp.17-18, 1997 that a silicon nitride film 140 is formed on the bit lines 106 in the wiring trench 127a being formed by the damascene method. According to the structure shown in FIG. 3, upon forming the storage contact holes 109 in the first, second, and third interlayer insulating film 123, 126, 129 made of silicon oxide or impurity containing silicon oxide, the silicon nitride film 140 formed on the bit lines 106 can act as an etching preventing layer. Accordingly, since the contact between the storage contact hole 130 and the bit lines 106 can be prevented by the silicon nitride film 140, the storage contact holes 130 can be formed in the self-align fashion.
By the way, if the wirings 106a, 113, 115 are formed thick to reduce resistances of the wirings 106a, 113, 115 in the peripheral circuit region 102, the bit lines 106 that have the same structure as the wirings 106a, 113, 115 are also formed thick. Therefore, there is such a problem that capacitances between the bit lines 106 are increased. However, since the storage contact holes 130 are formed deeper as the bit lines 106 are formed thicker in FIG. 3, it is difficult to bury the storage contact plugs 131 into the storage contact holes 109. In other words, if an aspect ratio of the storage contact hole 109 is increased, there is the possibility that coverage of conductive material being filled into the storage contact holes 109 becomes worse. In contrast, such an approach may be thought of that forming positions of the bit lines 106 in the memory cell region 101 and the wirings 106a, 113, 115 in the peripheral circuit region 102 are lowered in height. But this approach is not practical since distances from the wirings 106a, 113, 115 to the word lines 105 and the lower wiring 114 must be assured to some extent.
In FIG. 3, the same references as those in FIG. 2 denote the same elements.
In order to overcome such problem, the structure in which the wirings in the peripheral circuit region are formed thicker than the bit lines is set forth in Patent Application Publication (KOKAI) Hei 10-200075 (U.S. Pat. No. 6,037,207) and Patent Application Publication (KOKAI) Hei 10-223858.
FIG. 4 to FIG. 7 are sectional views showing the structures of the bit lines and the wirings set forth in Patent Application Publication (KOKAI) Hei 10-200075 respectively, and the same references as those in FIG. 2 denote the same elements.
In FIG. 4, the bit lines 141 are formed on the first interlayer insulating film 123 and are also connected to the impurity diffusion layers 103a in the memory cell region 101 via the first contact plugs 125a. Then, a first wiring 141a extended from the bit lines 141 to the peripheral circuit region 102 is connected to one impurity diffusion layer 112a in the active region 110 via the contact hole 128b. Also, in the peripheral circuit region 102, a second wiring 142 is formed on the first interlayer insulating film 123 and then the second wiring 142 is connected to the other impurity diffusion layer 112b in the active region 110 via the contact hole 128c. 
The bit lines 141 and the first and second wirings 141a, 142 are formed by patterning the same metal film. That is, they are formed via steps of reducing the film thickness of the overall metal film in the memory cell region 101 and the metal film in a part of the peripheral circuit region 102 by etching these metal films using a first resist mask, and then etching simultaneously the metal films in the memory cell region 101 and the peripheral circuit region 102 using a second resist mask. Accordingly, the film thickness of the bit lines 141 in the memory cell region 101 and the first wiring 141a in the peripheral circuit region 102 is reduced smaller than that of the other wiring 142 in the peripheral circuit region 102.
The bit lines 141 in the memory cell region 101 and the first wiring 141a in the peripheral circuit region 102 shown in FIG. 5 is smaller in thickness than the second wiring 142 in the peripheral circuit region 102, like those shown in FIG. 4. However, an upper surface of the first interlayer insulating film 123 under the bit lines 141 and the first and second wirings 141a, 142 has different heights in the memory cell region 101 and the peripheral circuit region 102, and thus a level difference 123a exists between these regions 101 and 102. This level difference 123a is formed by the etching using a resist mask. The metal film formed on the first interlayer insulating film 123 is polished by the CMP method and then patterned into shapes of the bit lines 141 and the first and second wirings 141a, 142. Accordingly, the bit lines 141 and the first wiring 141a are smaller in height than the second wiring 142, but upper surfaces of the bit line 141 and the first and second wirings 141a, 142 are identical in height.
FIGS. 6A and 6B show steps of forming the bit lines 141 and the first and second wirings 141a, 142 on the first interlayer insulating film 123 that has the level difference 123a like FIG. 5. That is, as shown in FIG. 6A, contact holes are formed on the impurity diffusion layers 103a, 112a, 112b in the memory cell region 101 and the peripheral circuit region 102 respectively by patterning the first interlayer insulating film 123. Then, plugs 125a, 143a, 143b made of polysilicon are buried in the contact holes, and then the same level difference 123a as that in FIG. 5 is formed on the first interlayer insulating film 123 by using a resist mask. In this case, a part of the plug 143b in the peripheral circuit region 102 is also etched simultaneously. Then, a silicon nitride film 144 and a silicon oxide film 145 are formed in sequence on the first interlayer insulating film 123, and then the silicon oxide film 145 is planarized by the CMP method. After this, as shown in FIG. 6B, a first wiring trench 145a and a second wiring trench 14b are formed in the memory cell region 101 and the peripheral circuit region 102 respectively by patterning the silicon oxide film 145 and the silicon nitride film 144 in sequence. In this case, since the silicon nitride film 144 can act as the etching stopper film, depths of the first wiring trench 145a and the second wiring trench 145b become different. In addition, a metal film is filled into the first wiring trench 145a and the second wiring trench 145b, and thus the bit lines 141 and the first wiring 141a are formed in the first wiring trench 145a and also the second wiring 142 that is thicker than the bit lines 141 is formed in the second wiring trench 145b. 
In FIGS. 6A and 6B, the same references as those in FIG. 2 denote the same elements.
In the meanwhile, the structure similar to those in FIGS. 6A and 6B is set forth in Patent Application Publication (KOKAI) Hei 10-223858. Since the silicon nitride film 144 is left in this structure, the step of forming contact holes by patterning the silicon nitride film 144 and the first interlayer insulating film 123 is employed after the first wiring trench 145a and the second wiring trench 145b are formed.
The bit lines 141 and first and second metal films 146, 147 shown in FIG. 7 are formed by the following method. That is, contact holes are formed on the impurity diffusion layers 103a, 112a, 112b in the memory cell region 101 and the peripheral circuit region 102 respectively by etching the first interlayer insulating film 123. Then, plugs 125a, 143a, 143b made of polysilicon are buried in the contact holes, and then a first metal film 146 is formed on a flat surface of the first interlayer insulating film 123. Then, a silicon oxide film 148 is formed on the first metal film 146 in the memory cell region 101 and also a second metal film 147 is formed on the first metal film 146 in the peripheral circuit region 102. Then, the bit line 141 and the wirings 141a, 142 are formed by patterning successively the first metal film 146, the second metal film 147 and the silicon oxide film 148. Accordingly, the thin bit lines 141 consisting of the first metal film 146 are formed in the memory cell region 101, and also the thick wirings 142 consisting of the first metal film 146 and the second metal film 147 are formed in the peripheral circuit region 102.
In FIG. 7, the same references as those in FIG. 2 denote the same elements.
By the way, according to the structure shown in FIG. 4, the metal film formed in the memory cell region 101 is thinned by selectively etching, and then the overall metal film is patterned simultaneously by the photolithography method. Therefore, since either the thin region or the thick region of the metal film is defocused when the photoresist used in patterning the overall metal film is exposed, such structure is undesirable for miniaturization. In addition, since both the thin region and the thick region of the metal film are etched in the same time upon patterning the overall metal film, side etching is caused in the thin region of the metal film and therefore conversion difference between the metal pattern (bit lines) in the memory cell region 101 and the metal pattern (wirings) in the peripheral circuit region 102 is easily caused.
Also, according to the structure shown in FIG. 5, difference in film thickness is provided to the metal films constituting the bit lines 141 and the first and second wirings 141a, 142, but their upper surfaces are made flat. Therefore, the problem of the defocusing of the resist formed on the metal film in exposure can be overcome. However, if the overall metal film having level difference on its lower side is patterned by the photolithography method, the thin region of the metal film is excessively etched to generate the side etching.
In addition, since respective upper surfaces of the bit lines 141 and the first and second wirings 141a, 142 are made flat, a position of the upper surfaces of the bit lines 141 becomes high if the second wiring 142 is formed thick. As a result, if the silicon nitride 140 shown in FIG. 3 is formed on the bit lines 141, the storage contact holes passing through between the bit lines 141 become deeper.
According to FIG. 4 and FIG. 5, it can be understood that, if the method of forming the bit lines and the wirings by patterning the metal film in which level difference is formed on the upper surface or the lower surface is employed, the improvement of the pattern precision of the bit lines cannot be achieved.
Further, according to the structure shown in FIG. 6A, in order to form the wiring trenches 145a, 145b having a different depth, the step of forming the silicon nitride film 144 as the etching stopper film and the step of etching the silicon nitride film 144 are needed, and thus throughput of the wiring formation is lowered.
In Patent Application Publication (KOKAI) Hei 10-223858 in which the structure similar to that shown in FIG. 6B is set forth, the silicon nitride film 144 serving as the etching stopper film is left. In this case, since the step of etching the silicon nitride film 144 and the first interlayer insulating film 123 by using two kinds of etchant is needed in the step of forming the contact holes used to connect the overlying bit lines 141 and the first and second wirings 141a, 142 to the impurity diffusion layers 103a, 112a, 112b, reduction in the throughput is inevitable.
Besides, according to the structure shown in FIG. 7, since the resist used upon patterning the first and second metal films 146, 147 and the silicon oxide film 148 is formed on the surfaces having the same height as the insulating film 148 and the second metal film 147, the problem of defocusing in the resist exposure is not caused. However, since different materials of the insulating film and the metal film are etched simultaneously after this, two kinds of etchant must be employed. In other words, since first the silicon oxide film 148 is etched and then the first and second metal films 146, 147 are patterned simultaneously, over-etching of the first metal film 146 serving as the bit lines is inevitable. In addition, the connection interface is present between the first metal film 146 and the second metal film 147 and thus the contact resistance is generated on the interface. Therefore, such structure is disadvantageous to reduction in the lower resistance of the wiring 142 in the peripheral circuit region 102.
It is an object of the present invention to provide a semiconductor device capable of increasing the pattern precision of the bit lines and the wirings which have a different film thickness, and reducing resistances of the bit lines and the wirings by forming shallow through holes that are formed between the bit lines in the self-alignment manner, and also improving lower resistance and throughput of the bit lines and the wirings, and a method of manufacturing the same.
According to the present invention, the depth of the first wiring trenches formed in the first region (memory cell region) of the first insulating film formed on the semiconductor substrate is set substantially equal to the depth of the second wiring trenches formed in the second region (peripheral circuit region), and the film thickness of the first wirings buried in the first wiring trenches is set thinner than that of the second wirings buried in the second wiring trenches, and the second insulating film is formed on the thinned first wirings.
Accordingly, there is no necessity to differentiate depths of a plurality of wiring trenches in the first region and the second region. Thus, the step of forming the etching stopper layer (silicon nitride film) to change the depths of the wiring trenches and the step of selectively etching the etching stopper layer can be omitted, and thus the reduction in throughput can be prevented.
Also, since the film thickness of the first wirings formed in the first wiring trenches and the film thickness of the second wirings formed in the second wiring trenches can be adjusted by thinning the first wirings, there is no need to form twice the same conductive film in the second wiring trenches by separate steps. Thus, the contact interface does not exist in the same conductive film, and the increase in resistance of the second wirings can be prevented.
Further, since the second insulating film (e.g. the silicon nitride film) covering the first wirings in the first region is buried only in the upper portions of the first wiring trenches, the upper surfaces of the second insulating film are substantially equal in height to the upper surfaces of the second wirings in the second region. Thus, the upper surfaces of the holes formed between a plurality of first wirings in the self-alignment manner can be set equal in height to the upper surfaces of the second wirings in the second region. Therefore, the holes can be formed shallow not to position higher than the second wirings, and thus the coverage of the conductive film buried in the holes as the plugs can be improved.
Moreover, after the pattern formation and the film thickness adjustment of the first wirings and the second wirings have been completed, the second insulating film formed on the first wirings can be formed. Therefore, it is not needed that the patterning of the second insulating film and the patterning of the first and second wirings should be carried out successively. Thus, tapering-off of the first wirings due to the over-etching is not caused. As a result, the pattern precision of the first wirings that are formed thinner than the second wirings can be improved.